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  • Report: High-k on High-micro--III-V MOSFETs enabled by atomic layer deposition
  • Release time:2011-05-17 clicks:1
  • High-k on High-micro -- III-V MOSFETs enabled by atomic layer deposition
    Professor:Peide (Peter) Ye
    Time: 8/10/2009 10:00am
    Place:A722

     

    High-k on High-micro -- III-V MOSFETs enabled by atomic layer deposition
    Peide (Peter) Ye
    School of Electrical and Computer Engineering and Birck
    Nanotechnology Center, Purdue University

    Abstract
    For the first time, high-performance III-V MOSFETs with
    nanoscale high-k gate dielectrics grown by atomic layer
    deposition (ALD) are demonstrated. The novel application of
    the ALD process on III-V compound semiconductors affords
    tremendous functionality and opportunity by enabling the
    formation of high-quality gate oxides and passivation layers
    on III-V devices. A 0.4-米m gate-length inversion-mode
    n-channel Al2O3/InGaAs MOSFET shows a gate leakage current
    density less than 10-4A/cm2, a record high maximum drain
    current of 1.05 A/mm and a peak transconductance of 0.35
    S/mm. The transconductance is improved to 1.3 S/mm at deep
    sub-micron gate-length. The mid-gap interface trap density
    (Dit) of high-k/GaAs and InGaAs is at the range of
    1011-1012/cm2-eV. The InGaAs MOSFETs show the promise for
    future high-speed low-power logic applications by
    benchmarking the state-of-the-art Si MOSFETs. The review of
    this work can be found in IEEE Spectrum September 2008 and
    Science February 2009.

    Peide (Peter) Ye received the B.S. degree in electrical
    engineering from Fudan University, Shanghai, China, in 1988
    and Ph.D. in solid state physics from Max-Planck-Institute
    of Solid State Research, Stuttgart, Germany, in 1996. From
    1996 to 2000, he was research fellow at NTT Basic Research
    Laboratories and NHMFL/Princeton University. He joined Bell
    Laboratories, Murray Hill, NJ and then Agere Systems in 2001
    as a Member of Technical Staff and becomes a Senior Member
    of Technical Staff in 2003. He is currently associate
    professor of electrical and computer engineering at Purdue
    University. His research activities include semiconductor
    physics and devices, nano-structures and nano-fabrications,
    quantum and spin transport, atomic layer deposition, III-V
    MOSFETs, and recently graphene based nanoelectronics.